interrupts-and-exceptions-baremetal

Interrupts and Exceptions (Bare-Metal)

Purpose

Guide agents through bare-metal interrupt handling on ARM Cortex-M: NVIC configuration, ISR writing rules, exception handlers (HardFault, BusFault), priority grouping, nesting, tail-chaining, and latency considerations.

When to Use

• Configuring peripheral IRQ priorities
• Writing ISRs that must not block
• Debugging HardFault after enabling interrupts
• Sharing data between ISR and main loop
• Optimizing interrupt latency

Workflow

1. NVIC overview (Cortex-M)

Exception / IRQ flow
├── NVIC receives IRQ (priority compare with BASEPRI/PRIMask)
├── Stacking: automatic save r0-r3, r12, lr, pc, psr
├── Branch to handler from vector table
├── Handler runs (should be short)
└── Unstack and return — tail-chain if another IRQ pending

2. Enable and prioritize an IRQ

#include "stm32f4xx.h"  /* CMSIS device header */
 
void uart_irq_init

Priority: lower numeric value = higher urgency (on most Cortex-M implementations). Check vendor docs for grouping bits.

3. ISR template

ISR rules:

• No blocking calls (printf, malloc, long loops)
• Minimize work — defer to main via flag/ring buffer
• Clear interrupt flags per datasheet (read-to-clear vs write-1-clear)

4. Critical sections

Or raise BASEPRI to mask lower-priority IRQs only.

5. HardFault handler

Decode CFSR/HFSR registers for fault cause:

6. Latency and tail-chaining

Measure with GPIO toggle + scope, or DWT cycle counter (DWT->CYCCNT).

7. Agent usage examples

Common Problems

Related Skills

• skills/baremetal/baremetal-startup — vector table entries
• skills/baremetal/uart-serial-baremetal — UART IRQ handlers
• skills/embedded/openocd-jtag — GDB breakpoint in ISR
• skills/debuggers/gdb — examine fault stack frame
• skills/low-level-programming/assembly-arm — fault handler asm